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NCP345
V CC
(5)
IN
(4)
V CC
Pre?
V5
regulator
R1
?
+
?
+
COMP
R3
UVLO
LOGIC
BLOCK
V CC
ON/OFF
DRIVER
OUT
OUT
(1)
R2
R4
Bandgap
Reference
CNTRL
(3)
GND
(2)
Figure 2. Detailed Block Diagram
PIN FUNCTION DESCRIPTIONS
Pin #
1
2
3
4
5
Symbol
OUT
GND
CNTRL
IN
V CC
Pin Description
This signal drives the gate of a P?channel MOSFET. It is controlled by the voltage level on IN or the logic state
of the CNTRL input. When an overvoltage event is detected, the OUT pin is driven to within 1.0 V of V CC in
less than 1.0 m sec provided that gate and stray capacitance is less than 12 nF.
Circuit Ground
This logic signal is used to control the state of OUT and turn?on/off the P?channel MOSFET. A logic High
results in the OUT signal being driven to within 1.0 V of V CC which disconnects the FET. If this pin is not used,
the input should be connected to ground.
This pin senses an external voltage point. If the voltage on this input rises above the overvoltage threshold
(VTH), the OUT pin will be driven to within 1.0 V of V CC , thus disconnecting the FET. The nominal threshold
level is 6.85 V and this threshold level can be increased with the addition of an external resistor between IN
and V CC .
Positive Voltage supply. If V CC falls below 2.8 V (nom), the OUT pin will be driven to within 1.0 V of V CC , thus
disconnecting the P?channel FET.
TRUTH TABLE
IN
<V th
<V th
>V th
>V th
CNTRL
L
H
L
H
OUT
GND
V CC
V CC
V CC
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